Information processing apparatus and media storage apparatus using the same

ABSTRACT

An information processing apparatus switches a clock to reduce power consumption of an information processing unit. In order to reduce an overhead time in switching, the information processing apparatus includes an interrupt controller for generating a clock switch signal by accepting an interrupt to each information processing unit and a clock switch circuit for switching the clock to be supplied to the information processing unit. Using a hardware interrupt signal to switch the clock to be supplied to circuits, the circuit clock can be switched real time, and reduction of the power consumption can be achieved.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2004-150582, filed on May 20,2004, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to information processing apparatus whichswitches an operation clock depending on necessity to reduce powerconsumption, and a media storage apparatus using the same.

2. Description of the Related Art

With the development of data processing technology in recent years,peripheral apparatus, such as magnetic disk apparatus, each having aprocessor and is operated by a firmware program, are increased. Inso-called information processing apparatus operated by such a processor,each individual circuit operates in synchronization by receiving aclock.

As high-speed information processing apparatus has been required inrecent years, in particular, processors, operating at high speed using afast clock are becoming in use, as well as peripheral circuits connectedto the processor. Such a fast clock is accompanied with an increase ofpower consumption and heat quantity. Meanwhile, when the informationprocessing apparatus is operated with an external power supply, abattery, etc., reduction of power consumption is required in theinformation processing apparatus.

As a method for realizing both high speed and low power consumption inthe information processing apparatus, it is effective to employ such amethod that, when there is no request for processing during operation ofthe information processing apparatus, the clock supply is eitherswitched to a low-speed clock, or suspended; and when the request forprocessing arises, the clock is restored to a high-speed clock, or theclock supply is restarted.

Conventionally, the above-mentioned clock switch operation has beenperformed in such a way that, when the processor supplied with thelow-speed clock receives an interrupt request, the request is recognizedby firmware processing (interrupt processing), and a clock mode registeris set to a high-speed mode. Thus, a clock gate is switched, therebyhigh-speed clock is supplied, as an example, in the Japanese Laid-openPatent Publication No. Hei-8-087818.

According to the conventional method of switching the clock by thefirmware, clock switching can be performed as a part of firmwareinterrupt processing, and accordingly, no extra hardware is needed. Onthe other hand, a problem of an overhead time arises when switching theclock.

Namely, on receipt of the interrupt request, the processor interpretsthe request by firmware, performs clock switching processing as a partof the interrupt processing, sets the clock mode in the register, andfinally switches the clock. Thus, a considerable time is needed tocomplete the switching.

Therefore, the switching processed by firmware requires a certain timeperiod. Furthermore, since the above operation is performed while theprocessor is running with a low-speed clock, the processing itself isperformed at low speed, and it takes time to handle the interruptrequest before the inherent interrupt processing is performed with ahigh-speed clock. As a result, time responsibility against the interruptrequest becomes degraded, caused by the clock switching performed in alow power consumption state. This impedes the merit of switching over tothe high-speed clock.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provideinformation processing apparatus for reducing overhead of a switchingtime even when the clock is switched to obtain reduced powerconsumption, and a media storage apparatus using the informationprocessing apparatus.

It is another object of the present invention to provide informationprocessing apparatus for improving time responsibility against aninterrupt request even when the clock is switched to reduce the powerconsumption, and a media storage apparatus using the informationprocessing apparatus.

It is still another object of the present invention to provideinformation processing apparatus for improving time responsibility ofthe apparatus by switching to a clock suitable to individual circuits,even when the clock is switched to reduce the power consumption, and amedia storage apparatus using the information processing apparatus.

In order to achieve the aforementioned objects, according to the presentinvention, information processing apparatus which performs informationprocessing by receiving a clock is disclosed. The information processingapparatus includes: an information processing apparatus which performsinterrupt processing on receipt of an interrupt; an interrupt controlcircuit which generates a clock switch signal on receipt of theinterrupt; and a clock switch circuit which switches a clock frequencyto be supplied to the information processing apparatus according to theclock switch signal.

Further, according to the present invention, a media storage apparatusfor at least reading data stored in a media storage is also disclosed.The media storage apparatus includes a media storage unit for at leastreading the data stored in the media storage, and a controller forcontrolling the media storage unit according to an external instruction.The controller further includes: an information processing unit whichperforms interrupt processing on receipt of an interrupt; an interruptcontrol circuit which generates a clock switch signal on receipt of theinterrupt; and a clock switch circuit which switches a clock frequencyto be supplied to the information processing unit according to the clockswitch signal.

Still further, according to the present invention, preferably the clockswitch circuit further includes: a first circuit which generates arelatively fast clock; a second circuit which generates a relativelyslow clock; and a switch circuit which switches from the slow clock tothe fast clock according to the clock switch signal.

Further, according to the present invention, preferably the clock switchcircuit further includes a circuit which generates the clock, and aswitch circuit which permits outputting the clock, according to theclock switch signal.

Still further, according to the present invention, preferably theinformation processing unit clears the clock switch signal of theinterrupt control circuit, on completion of the interrupt processing.

Further, according to the present invention, preferably the interruptcontrol circuit receives a plurality of interrupts, and selectivelygenerates the clock switch signal according to each kind of theplurality of interrupt factors.

Further, according to the present invention, preferably the interruptcontrol circuit further includes a first interrupt status register foraccepting a plurality of interrupts, and a second interrupt statusregister for clock switching for generating the clock switch signal fromthe first interrupt status register. According to the acceptance of theinterrupt, the information processing unit clears the accepted interruptin the first interrupt status register on acceptance of the interrupt,and clears the second interrupt status register for clock switching, oncompletion of the interrupt processing.

Further, according to the present invention, preferably the interruptcontrol circuit further includes a selector being disposed between thefirst interrupt status register and the second interrupt status registerfor clock switching, for selecting an interrupt to be set from the firstinterrupt status register to the second interrupt status register,according to the plurality of interrupt factors.

Further, according to the present invention, preferably the clock switchcircuit further includes a plurality of clock switch circuits eachcorresponding to each circuit constituting the information processingunit.

Still further, according to the present invention, preferably the clockgeneration circuit in the clock switch circuit includes a programmableclock divider of which division ratio is programmable.

Further scopes and features of the present invention will become moreapparent by the following description of the embodiments with theaccompanied drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a configuration diagram of information processing apparatusaccording to one embodiment of the present invention.

FIG. 2 shows a diagram illustrating a clock switch circuit shown in FIG.1.

FIG. 3 shows a processing flowchart of the interrupt processing shown inFIG. 1.

FIG. 4 shows an explanation diagram of the interrupt processing shown inFIG. 3.

FIG. 5 shows a configuration diagram of a clock switch circuit accordingto another embodiment of the present invention.

FIG. 6 shows a configuration diagram of a clock switch circuit accordingto still another embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The preferred embodiment of the present invention is describedhereinafter, on the order of information processing apparatus, clockswitching method, and other embodiments, by referring to the charts anddrawings. However, it is noted that the scope of the present inventionis not limited to the embodiments described below.

Information Processing Apparatus

FIG. 1 shows a configuration diagram of a media storage apparatus usinginformation processing apparatus according to one embodiment of thepresent invention. FIG. 2 shows a diagram illustrating a clock switchcircuit shown in FIG. 1.

In FIG. 1, as an example of the information processing apparatus, acontroller of a magnetic disk apparatus (HDD) which reads/writes datafrom/to a magnetic disk, which is a media storage apparatus, is shown.As shown in FIG. 1, a magnetic disk apparatus 10 is connected to a host(not shown) such as a personal computer by a cable 9 having an interfaceconforming to the ATA (AT Attachment) standard.

As shown in FIG. 1, the magnetic disk apparatus 10 includes a magneticdisk 19, a spindle motor 20 for rotating the magnetic disk 19, amagnetic head 25 for reading/writing data from/to the magnetic disk 19,and an actuator (VCM) 22 for moving the magnetic head 25 in the radius(cross-track) direction of the magnetic disk 19.

Further, as the controller, a HDC (hard disk controller) 26, a databuffer 14, a MPU 11, a memory (RAM) 13, and a nonvolatile memory (F-ROM)27 are provided. Also, as a drive controller, a read channel circuit 29,a head IC 18, and a servo controller 28 are provided.

The servo controller 28 is provided with a spindle motor driver 21, aVCM driver 23, a position detector 24, and a DSP 38. Here, HDC 26, MPU11, RAM 13, F-ROM 27 and the servo controller 28 are connected by a bus17.

HDC 26 includes an ATA interface controller 12 having a task file 12A towhich the host sets a task, a data buffer controller 15 for controllingthe data buffer 14, and a formatter controller 16 for controlling therecording data format.

The read channel circuit 29 selects a magnetic head for reading orwriting data according to an instruction from HDC 26. When reading, theread channel circuit 29 receives read data from the magnetic head, andwhen writing, supplies write data to the magnetic head. The head IC 18makes recording current flow to the magnetic head 25 according to therecording data, and outputs read data (including servo information)after amplifying a read signal output from the magnetic head 25.

The position detector 24 detects a position of the magnetic head 25 fromthe servo information fed from the head IC 18. The spindle driver 21drives the spindle motor 20 to rotate. The VCM driver 23 drives the VCM(voice coil motor) 22 to move the magnetic head 25. DSP (digital signalprocessor) 38 performs position control of VCM 22 via VCM driver 23, soas to control the position of the magnetic head 25 to a target position,using a present position received from the position detector 24 and thetarget position received from MPU (microprocessor) 11.

MPU 11 performs position control, read/write control, and retry controlof the magnetic head 25. Memory (RAM) 13 stores data necessary for theprocessing of MPU 11. Nonvolatile memory 27 stores processing program ofMPU 11 and firmware.

MPU 11 and RAM 13 are housed in an MPU block 30. As shown in FIG. 2 indetail, this MPU block 30 includes a PLL (phase lock loop) circuit 33for generating a reference clock; an interrupt controller 35 forgenerating interrupt from an interrupt signal fed from a plurality ofinterrupt signal lines; and a clock switch circuit 34 for switching theclock to be supplied to MPU 11 and peripheral circuits in HDC 26, etc.caused by an interrupt from the interrupt controller 35.

As shown in FIG. 2, the clock switch circuit 34 is constituted of aplurality of clock switch circuits 34-1 to 34-m each corresponding toeach operation frequency of individual circuits (for example, MPU 11,and the interface circuit 12 and the buffer controller 15 in HDC 26).

Each clock switch circuit 34-1 to 34-m includes a pair of programmableclock dividers 340, 342 for dividing the reference clock (PLL output) ofthe PLL circuit 33 at a programmed division ratio, and a multiplexer344. The programmable clock divider 340 outputs a high-speed clock(which is referred to as fast clock), with the division ratio being set,for example, to 1:1. In contrast, the program clock divider 342 outputsa low-speed clock (which is referred to as slow clock), with thedivision ratio being set, for example, to 1:n.

In this example, the clock switch circuit 34-1 can output either thefast clock, or the slow clock having a frequency of 1/n of the fastclock. The multiplexer 344 outputs the slow clock in normal cases, whileoutputs the fast clock while the interrupt signal is being set to thehigh level.

Meanwhile, the interrupt controller 35 includes a priority controller350 for controlling the priority of a plurality of interrupt factors(signals); a first interrupt status register 352 for storing each stateof the interrupt factors; a set-enable selector 354; a second interruptstatus register (for switching to the fast clock) 356; and an OR circuit358 for outputting an interrupt-signal (clock switch signal) for thefast clock to the clock switch circuit 34, by ORing each register of theinterrupt status register (for switching to the fast clock) 356.

Interrupt factors to MPU 11 includes a timer interrupt, a serialtransfer interrupt (UART), and a host interrupt. When a plurality ofinterrupt request are received simultaneously, the priority controller350 gives priority to one interrupt request according to a predeterminedpriority order, and sets an interrupt state to a corresponding registerof the status register 352.

Also, the interrupt to which the priority is given is notified to MPU11. This interrupt status register 352 is cleared when the interruptprocessing is completed in MPU 11. MPU 11 sets set-enable selector 354in advance so that a type of interrupt to be switched to the fast clockis set to ‘enable’. Among interrupt factors set in the interrupt statusregister 352, an interrupt enabled by the set-enable selector 354 is setto the interrupt status register (for switching to the fast clock) 356.

This interrupt status register (for switching to the fast clock) 356 iscleared by MPU 11, on completion of the interrupt processing. Theregister contents for each interrupt factor in the interrupt statusregister (for switching to the fast clock) 356 are ORed in the ORcircuit 358, and the OR result outputs to the clock switch circuit 34.

Namely, when any interrupt signal is being input, the multiplexer 344 inthe clock switch circuit 34 selects a clock having the division ratio of1/1. In contrast, when no interrupt signal is being input, themultiplexer 344 selects a clock having the division ratio of 1/n. Theselected clock is supplied as circuit clock. In this circuit, circuitclock supply can be selected.

For example, in case of FIG. 1, as to the fast clock frequencies, 133MHz for MPU 11, 100 MHz for ATA interface circuit 12A, and 66 MHz fordata buffer 14 are applied, respectively.

Clock Switching Method

FIG. 3 shows a processing flowchart of the interrupt processing in MPU11, illustrating a clock switching method according to one embodiment ofthe present invention. FIG. 4 shows an explanation diagram of theoperation according to the above clock switching method. Hereafter,referring to FIG. 4, the processing shown in FIG. 3 will be described.

(S10) As shown in FIG. 4, in a state that no interrupt signal is input,the multiplexer 344 in the clock switch circuit 34 selects the slowclock of the programmable clock divider 342. As shown in FIG. 4, on theoccurrence of an interrupt factor, the priority controller 350 gives thepriority to one interrupt according to the predetermined priority order,as described earlier, and sets an interrupt state into a correspondingregister of the interrupt status register 352.

The interrupt to which the priority has been given is accepted in MPU11. In the set-enable selector 354, the interrupt ‘enabled’ by theset-enable selector 354 is set to the interrupt status register (forswitching to the fast clock) 356.

The contents of each registers for each interrupt in the interruptstatus register (for switching to the fast clock) 356 are ORed in the ORcircuit 358, and OR result outputs to the multiplexer 344 in the clockswitch circuit 34. The multiplexer 344 selects the fast clock in theprogrammable clock divider 340. Thus, as shown in FIG. 4, MPU 11, HDC26, etc. operate with the fast clock.

(S12) When MPU 11 accepts the interrupt, MPU 11 clears the interruptstatus in the interrupt status register 352 of the interrupt controller35. At this time, the interrupt status register (for switching to thefast clock) 356 is not cleared. Accordingly, the multiplexer 344continues selecting the fast clock of the programmable clock divider340.

(S14) MPU 11 then executes interrupt processing corresponding to theabove interrupt content.

(S16) When MPU 11 completes the interrupt processing corresponding tothe interrupt factor, MPU 11 clears the interrupt status in theinterrupt status register (for switching to the fast clock) 356. Withthis, the multiplexer 344 is returned from the fast clock selectionstate by the programmable clock divider 340 to the slow clock selectionstate by the programmable clock divider 342. Thus, as shown in FIG. 4,the slow clock is supplied to MPU 11, HDC 26, etc.

As such, the conventional method of switching the clock by firmware isreplaced by a method of switching the circuit clock using a hardwareinterrupt signal, according to the present invention. Thus, the circuitclock is switched real time, enabling reduced power consumption.Further, since firmware processing using the slow clock is not requiredto switch the clock, the response speed against interrupt in theinformation processing apparatus (MPU, HDC, etc.) can be improved.

Moreover, by using the set-enable selector 354, it becomes possible tospecify an interrupt factor which is not required to set to theinterrupt status register (for switching to the fast clock) 356,according to the interrupt factor. Accordingly, on the occurrence of aninterrupt cause which does not require fast processing, use of the slowclock may be continued. Namely, on the occurrence of an interrupt,different circuit clock can be set according to the interrupt factor.

In particular, in the case of peripheral apparatus such as a magneticdisk apparatus and a printer, because such apparatus has mechanicalportions, quantity of power consumed is relatively large, and in somecases, the power is supplied externally. Therefore, the effect of lowerpower consumption becomes large even when an improved time of clockswitch time is relatively small.

Other Embodiments

FIG. 5 shows a configuration diagram of a clock switch circuit accordingto another embodiment of the present invention. In FIG. 5, only clockswitch circuit 34 is illustrated, while the interrupt controller 35 isidentical to the interrupt controller shown in FIG. 2.

As shown in FIG. 5, the clock switch circuit 34 includes a plurality ofclock switch circuits 34-1 to 34-m, corresponding to the operationfrequency of each circuit (for example, MPU 11, and interface circuit 12and buffer controller in HDC 26).

Each clock switch circuit 34-1 to 34-m includes a single programmableclock divider 346 for dividing the reference clock (PLL output) of PLLcircuit 33 at a programmed division ratio, and a gate 348. Theprogrammable clock divider 346 is provided for outputting a high-speedclock (fast clock), with the division ratio being set, for example, to1:1.

In this example, the clock switch circuit 34-1 can either output orsuspend the fast clock, which is controllable by the gate 348corresponding to an interrupt signal. Namely, the clock switch circuit34-1 outputs the fast clock while the interrupt signal is being set tothe high level.

In the above another embodiment also, the circuit clock is suspendedusing a hardware interrupt signal. Thus, the circuit clock is switchedreal time, enabling reduced power consumption more than ever.

Moreover, conventionally, the clock switching is performed usingfirmware, and therefore the MPU clock has to be input at any time.However, inherently, in case that no circuit operation is required,namely in the state of no occurrence of interrupt, inputting the circuitclock is not necessary. Therefore, by completely suspending the clock,further reduction of the power consumption can be achieved.

FIG. 6 shows still another embodiment of the present invention, in whichthe configuration diagram of a clock switch circuit according to thisembodiment is illustrated. In FIG. 6, the like parts shown in FIG. 5 areshown by the like symbols. Only clock switch circuit 34 is illustratedhere, since the configuration of the interrupt controller 35 isidentical to that shown in FIG. 2.

As shown in FIG. 6, the clock switch circuit 34 includes a plurality ofclock switch circuits 34-1 to 34-m, corresponding to the operationfrequency of each circuit (for example, MPU 11, and interface circuit 12and the buffer controller 15 in the HDC 26) for each interrupt factor.

Similarly to FIG. 5, each clock switch circuit 34-1 to 34-m includes asingle programmable clock divider 346 for dividing the reference clock(PLL output) of the PLL circuit 33 at a programmed division ratio, and agate 348. The programmable clock divider 346 outputs fast clocks ofdifferent frequencies from each clock switch circuit 34.

In this example also, the gate 348 controls an output or suspend of fastclock of the clock switch circuits 34-1 to 34-m according to interruptsignal. Namely, each clock switch circuit 34-1 to 34-m outputs the fastclock while the interrupt signal is being set to the high level.

Furthermore, an interrupt priority controller 410 and a multiplexer 400are provided for the interrupt control, by which the circuit clockfrequency to be supplied to each circuit is switched according to eachinterrupt factor.

Namely, the interrupt priority controller 410 determines the interruptfactor from the content of interrupt status register (for switching tothe fast clock) 356 shown in FIG. 2, and selects the multiplexer 400.The multiplexer 400 switches each output of clock switch circuit 34-1 to34-m using the selection signal fed from the interrupt prioritycontroller 410, and supplies the clock to each circuit.

Each clock switch circuit 34-1 to 34-m outputs the clock of differentfrequency. Thus, in response to a plurality of multiple interrupts, itbecomes possible to supply the clock of different frequency according tothe interrupt factor, so that the frequency is suitable for each circuit(such as MPU 11) in view of balancing between the processing speed andthe low power consumption.

Namely, by providing the interrupt priority controller 410, the circuitclock can be selected to the maximum or the minimum value, or any other.Also, the embodiment produces the similar effect to the embodiment shownin FIG. 5.

In the configuration shown in FIG. 6, the interrupt priority controller410 directly receives the interrupt factors shown in FIG. 2. When amultiple interrupt occurs, the circuit clock of the maximum value isselected, so that a plurality of interrupts is processed successively.On the other hand, when no multiple interrupt occurs, for example incase of a single interrupt, the circuit clock of minimum value may beselected.

In the above-mentioned other embodiment, the information processingapparatus is exemplified by a magnetic disk controller. However, it maybe applicable to other storage apparatus such as the apparatus using anoptical disk, an optical magnetic disk, and other storage apparatususing other storage media. Also, the method according to the presentinvention may be applicable not only to the disk apparatus, but also toperipheral apparatus including other memory apparatus, printers, imageprocessing apparatus, etc. which are operated by the OS in theupper-level apparatus, as well as personal computers, portable terminalapparatus including portable telephones, information home appliances,etc.

Additionally, the interface is not limited to the ATA interface, and maybe applicable to other interfaces. Also, the present invention is alsoapplicable to a case of a single interrupt factor, though a plurality ofinterrupt factors have been illustrated in the foregoing description.Moreover, the interrupt factors may not be limited to the embodimentsshown above, and other kinds of interrupt factors are applicable.

According to the present invention, the conventional method of switchingthe clock by firmware is replaced by a method of switching the circuitclock using a hardware interrupt signal, enabling switching of thecircuit clock in real time with reduced power consumption. Further,since firmware processing using a slow clock is not required, it ispossible to obtain an improved response speed against the interrupts ininformation processing apparatus (MPU, HDC, etc.), which becomes of useto provide apparatus satisfying both low power consumption andhigh-speed time responsibility.

The foregoing description of the embodiments is not intended to limitthe invention to the particular details of the examples illustrated. Anysuitable modification and equivalents may be resorted to the scope ofthe invention. All features and advantages of the invention which fallwithin the scope of the invention are covered by the appended claims.

1. An information processing apparatus for performing informationprocessing by receiving a clock, comprising: an information processingunit which performs interrupt processing on receipt of an interrupt; aninterrupt control circuit which generates a clock switch signal onreceipt of the interrupt; and a clock switch circuit which switches aclock frequency to be supplied to the information processing unitaccording to the clock switch signal.
 2. The information processingapparatus according to claim 1, wherein the clock switch circuit furthercomprises: a first circuit which generates a relatively fast clock; asecond circuit which generates a relatively slow clock; and a switchcircuit which switches from the slow clock to the fast clock accordingto the clock switch signal.
 3. The information processing apparatusaccording to claim 1, wherein the clock switch circuit furthercomprises: a circuit which generates the clock; and a switch circuitwhich permits outputting the clock of the circuit, according to theclock switch signal.
 4. The information processing apparatus accordingto claim 1, wherein the information processing unit clears the clockswitch signal of the interrupt control circuit, on completion of theinterrupt processing.
 5. The information processing apparatus accordingto claim 1, wherein the interrupt control circuit receives a pluralityof interrupts, and selectively generates the clock switch signalaccording to each kind of the plurality of interrupt factors.
 6. Theinformation processing apparatus according to claim 4, wherein theinterrupt control circuit further comprises: a first interrupt statusregister for accepting a plurality of interrupts; and a second interruptstatus register for clock switching, for generating the clock switchsignal from the content of the first interrupt status register, andwherein the information processing unit clears the accepted interrupt inthe first interrupt status register when the information processing unitaccepts the interrupt, and clears the second interrupt status registerfor clock switching, on completion of the interrupt processing.
 7. Theinformation processing apparatus according to claim 6, wherein theinterrupt control circuit further comprises a selector disposed betweenthe first interrupt status register and the second interrupt statusregister for clock switching, which selects an interrupt to be set fromthe first interrupt status register to the second interrupt statusregister for clock switching, according to the plurality of interruptfactors.
 8. The information processing apparatus according to claim 1,wherein the clock switch circuit further comprises a plurality of clockswitch circuits each corresponding to each circuit constituting theinformation processing unit.
 9. The information processing apparatusaccording to claim 9, wherein the clock generation circuit in the clockswitch circuit comprises a programmable clock divider of which divisionratio is programmable.
 10. A media storage apparatus for at leastreading data stored in a media storage, comprising: a media storagemechanism for at least reading the data stored in the media storage; anda controller for controlling the media storage mechanism according to anexternal instruction, wherein the controller further comprises: aninformation processing unit which performs interrupt processing onreceipt of an interrupt; an interrupt control circuit which generates aclock switch signal on receipt of the interrupt; and a clock switchcircuit which switches a clock frequency to be supplied to theinformation processing unit according to the clock switch signal. 11.The media storage apparatus according to claim 10, wherein the clockswitch circuit further comprises: a first circuit which generates arelatively fast clock; a second circuit which generates a relativelyslow clock; and a switch circuit which switches from the slow clock tothe fast clock, according to the clock switch signal.
 12. The mediastorage apparatus according to claim 10, wherein the clock switchcircuit further comprises: a circuit which generates the clock; and aswitch circuit which permits outputting the clock of the circuit,according to the clock switch signal.
 13. The media storage apparatusaccording to claim 10, wherein the information processing unit clearsthe clock switch signal of the interrupt control circuit, on completionof the interrupt processing.
 14. The media storage apparatus accordingto claim 10, wherein the interrupt control circuit receives a pluralityof interrupts, and selectively generates the clock switch signalaccording to each kind of the plurality of interrupt factors.
 15. Themedia storage apparatus according to claim 13, wherein the interruptcontrol circuit further comprises: a first interrupt status register foraccepting a plurality of interrupts; and a second interrupt statusregister for clock switching, for generating the clock switch signalfrom content of the first interrupt status register, and wherein theinformation processing unit clears the accepted interrupt in the firstinterrupt status register when the information processing unit acceptsthe interrupt, and clears the second interrupt status register for clockswitching, on completion of the interrupt processing.
 16. The mediastorage apparatus according to claim 14, wherein the interrupt controlcircuit further comprises a selector disposed between the firstinterrupt status register and the second interrupt status register forclock switching, which selects an interrupt to be set from the firstinterrupt status register to the second interrupt status register forclock switching, according to the plurality of interrupt factors. 17.The media storage apparatus according to claim 10, wherein the clockswitch circuit further comprises a plurality of clock switch circuitseach corresponding to each circuit constituting the informationprocessing unit.
 18. The media storage apparatus according to claim 10,wherein the clock generation circuit in the clock switch circuitcomprises a programmable clock divider of which division ratio isprogrammable.